1. Field of the Invention
The present invention relates to a high frequency circuit for realizing a high efficiency power amplifier with a wide output power range which is suitable for use in a portable telephone or the like, for example, and a communication device using such a high frequency circuit.
2. Description of the Related Art
In general, the power amplifier has an efficiency which lowers at low output, because its power addition efficiency increases as the output power is increased and takes the maximum value in a vicinity of the saturation point of the output power. FIG. 1A shows an exemplary relationship between the efficiency and the output power at low output in a general amplifier. Here, the efficiency is a value obtained by dividing an RF (high output) output power by a DC (direct current) input power, which corresponds to a collector efficiency of a bipolar transistor and a drain efficiency of a field effect transistor. FIG. 1B shows an inverse of the efficiency shown in FIG. 1A in the logarithmic scale.
As shown in FIGS. 1A and 1B, the efficiency is sequentially degraded from 72% at the output power of 30 dBm (dBmW to be accurate, but will be abbreviated as dBm hereafter) to 21.8% at the output power of 20 dBm, 4.7% at the output of 10 dBm, and 1,5% at the output power of 5 dBm. Accordingly, a ratio of the DC input power with respect to the RF output power sequentially increases to 1.4 at the 30 dBm output, 4.6 at the 20 dBm output, 21.2 at the 10 dBm output, and 67.1 at the 5 dBm output.
The cause of this degradation of the efficiency at low output will now be explained using a simplified ideal transistor model. FIGS. 2A and 2B show graphs indicating a relationship between current and voltage in the alternating currents.
In FIGS. 2A and 2B, it is assumed that a load line is as indicated by a chain line KB, the output voltage is in a form of a sinusoidal wave with an average value set at a bias voltage, and the output current is in a form of a half-wave rectified wave Iout(t). Note that a point B in FIGS. 2A and 2B corresponds to the bias point.
FIGS. 2A and 2B show the case of the class B operation. The RF output power is given by a product of an effective value of the fundamental wave component Vout of the output power and an effective value of the fundamental wave component I1 (t). One half of an area of a rectangle with a point R and a point B as diagonal corners corresponds to the RF output power.
The DC input power is given by a product of the bias and an average value of the output current Iout(t), which corresponds to an area of a rectangle with a point D and a point B as diagonal corners (which will be referred to as a rectangle DB hereafter) in FIGS. 2A and 2B. The efficiency is given by a ratio of these two areas.
With respect to the case of FIG. 2A, in the case of FIG. 2B, the current amplitude and the voltage amplitude are both reduced to xc2xd so that the output power is xc2xc. On the other hand, the direct current is given by an average value of the RF current so that it is also reduced to xc2xd but the direct current voltage is fixed at a point B, so that the area of the rectangle DB is xc2xd. As a result, the efficiency is reduced to xc2xd whenever the RF output power is reduced to xc2xc (xe2x88x926 dB). In practice, a rate of the degradation of the efficiency is greater than xc2xd due to the influence of the knee voltage or the fact that the operation is actually the class AB operation.
Conventionally, one way of compensating such a degradation of the efficiency at low output is to use an amplifier circuit as shown in FIG. 3A.
Namely, as shown in FIG. 3A, in this conventional amplifier circuit, a plurality of amplifiers with different maximum output powers, AMP1 (with maximum output of xe2x88x9220 dBm) AMP2 (with maximum output of 5 dBm), and AMP3 (with maximum output of 30 dBm) are arranged in series, while bias circuits 75 and 76 are provided with respect to the AMP2 and AMP3 of the later stages, and a connection form is selected by switching switch circuits S71. S72, S73 and S74, so as to realize an appropriate power amplification.
However, as can be seen from a gain diagram shown in FIG. 3B, in the conventional amplifier circuit described above, there are cases for outputting the power that is lower by as much as 25 dB at most with respect to the maximum output power 30 dBm of AMP3 or the maximum output power 5 dBm of AMP2 in a range (B in FIG. 3B) of the output power between 5 dBm and 30 dBm, so that the degradation of the efficiency will be caused. Similarly, even in a range (D in FIG. 3B) of the output power between xe2x88x9220 dBm and 5 dBm, there is an increase of the consumed power due to the degradation of the efficiency although it is not as much as that in the range B described above.
Also, as shown in FIG. 3A, the gain of each stage is usually about 25 dB, so that it is difficult to improve the degradation of the efficiency considerably by the method described above. In this regard, it is also possible to consider a method using a greater number of amplification stages, but in such a case, the minimum unit for the amplification stages that is practically feasible is expected to be 10 dB to 15 dB corresponding to the gain per one stage of a transistor.
In this case, there is a need to align the input/output impedance of each stage, and a conversion up to a higher impedance may be required instead of the ordinarily required conjugate matching of adjacent transistors, which can cause an increase of losses or a complication of a circuit configuration.
For this reason, conventionally, a method for optimizing the load line of the amplifier of arbitrary stage according to the output power has been proposed. FIG. 4A shows a circuit for realizing this conventional optimization method schematically.
A circuit shown in FIG. 4A realizes a method for switching an effective transistor size of the amplifier, where a plurality of amplifiers 14a and 14b are connected in parallel, while input switches Si1 and Si2 and output switches So1 and So2 are provided at the input side and the output side of these transistors 14a and 14b respectively, and input signals entered from a variable matching circuit 13i are entered into a transistor with appropriate gate length or emitter area by switching the switches Si1, Si2, So1 and So2 and amplified signals are outputted to a variable matching circuit 130. At this point, the matching to a matching condition suitable for a respective transistor size is made by the variable matching circuits 13i and 13o. 
In such a conventional amplifier circuit, as a result of selectively combining a plurality of transistors 14a and 14b appropriately, the unnecessary power consumption can be reduced by reducing the number of transistors that are effective at low output power so as to reduce currents and vary the maximum value thereby maximizing the efficiency at the low output.
In the circuit shown in FIG. 4A, the maximum output power is reduced to xc2xd by reducing the transistor size to xc2xd, so that the efficiency can be maximized for the power in a narrow range of about 3 dB. However, in order to control a range as wide as 24 dB as in the case of FIGS. 3A and 3B, 24/3=8 so that as many as 28=256 of divided transistor cells would be required.
Also, in the circuit shown in FIG. 4A, there is a need to satisfy the matching condition even when the slope of the load line changes from BK1 to BK2, so that there is a need to change the matching circuit simultaneously. Such a variable matching circuit can be realized by any of a circuit shown in FIG. 5A in which a variable inductance 11 and a variable capacitor 12 are combined, a circuit shown in FIG. 5B in which distributed constant circuits 14 to 16 are connected through switches S1 and S2, and a circuit shown in FIG. 5C in which matching circuits 13a and 13b of different types are switched by switches Si11, Si12, So11 and So12. However, the mechanisms of these circuits are all complicated so that the increase of an implementation area can be caused. Also, there are losses in the switch, the variable inductance, and the variable capacity, so that their use in the matching circuit of the power amplifier is not preferable as they can cause a degradation of the efficiency.
Another way of compensating the degradation of the efficiency at low output is to use an amplifier circuit as shown in FIG. 6A. This amplifier circuit realizes a method for optimizing the power source voltage to be supplied to the amplifier according to the output power, where a voltage Vdc to be applied to a transistor 17 is adjusted by variable voltage sources 9 and 10 so as to move the bias point from B2 to B1 and change the load line from K2B2 to K1B1 as shown in FIG. 6B, such that the power and the voltage amplitude on the load line are maximized. In this case, the matching of input/output can be made by constant matching circuits 18i and 18o rather than variable matching circuits.
In the circuit shown in FIG. 6A, the continuous output power adjustment becomes possible, but as shown in FIG. 6B, the slope of the load lines (K1B1 and K2B2) remains unchanged so that the variable matching circuit is basically unnecessary, and the RF output power for realizing the maximum efficiency is lowered by about 6 dB when the power source voltage is simply reduced to xc2xd.
A variable voltage source with sufficiently high efficiency capable of supplying a large amount of currents to be consumed by the power amplifier can be realized by a step-down DC-DC converter as shown in FIG. 6C in which a resistance L and a capacitor C are appropriately connected by switches Q1 and Q2 controlled by a control circuit. However, the lowest output voltage is only about 1 V due to the reference voltage of the internal regulator, and the efficiency of the variable voltage source is degraded at the low voltage output, so that it is difficult to maintain the high efficiency over a wide output power range and there is also a problem that the implementation area is large.
Also, in the communications using the CDMA scheme, for example, there is a need to change the transmission output power according to a distance between a mobile station and a base station. This is because there is a need to align radio signals from a plurality of mobile stations at receiver input terminals of the base station. Similarly, it is preferable to align radio signals arriving from a plurality of base stations at receiver input terminals of the mobile station.
For this reason, the transmission power control is carried out in the communication system using the CDMA scheme, such that the transmission power varies within a range (dynamic range) of about 75 dB. Consequently, the power addition efficiency of the power amplifier is required to be high at the powers other than the maximum output power. The probability density function for the transmission powers is roughly in a form of the normal distribution, and the average transmission power of the mobile terminal is in a range of 10 dBm to 16 dBm, although it varies due to system related factors such as the arrangement of the base stations. Thus, there is a need to maintain a high power addition efficiency throughout a range of about 0 dBm (low output) to 30 dBm (high output).
It is therefore an object of the present invention to provide a high frequency circuit capable of realizing a power amplifier with a wide dynamic range in which it is hard to degrade the power addition efficiency at low output, using a simple circuit requiring a small implementation area, as well as a compact and lightweight communication device that can be realized by using such a high frequency circuit.
According to one aspect of the present invention there is provided a high frequency circuit, comprising: a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals; a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals; a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted.
According to another aspect of the present invention there is provided a communication device, comprising: at least one antenna configured to transmit or receive radio signals; at least one power amplifier configured to amplify the radio signals to be transmitted or received by the at least one antenna, including a high frequency circuit formed by: a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals; a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals; a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted; and a control unit configured to control the high output amplifier cell block and the low output amplifier cell block by putting either one of the high output amplifier cell block and the low output amplifier cell block in an amplification operation state and another one of the high output amplifier cell block and the low output amplifier cell block in a high impedance state.
Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.